FLOWER: A Comprehensive Dataflow Compiler for High-Level Synthesis

FPGAs have found their way into data centers as accelerator cards, making reconfigurable computing more accessible for high-performance applications. At the same time, new high-level synthesis compilers like Xilinx Vitis and runtime libraries such as XRT attract software programmers into the reconfigurable domain. While software programmers are familiar with task-level and data-parallel programming, FPGAs often require different types of parallelism. For example, data-driven parallelism is mandatory to obtain satisfactory hardware designs for pipelined dataflow architectures. However, software programmers are often not acquainted with dataflow architectures - resulting in poor hardware designs.

In this work we present FLOWER, a comprehensive compiler infrastructure that provides automatic canonical transformations for high-level synthesis from a domain-specific library. This allows programmers to focus on algorithm implementations rather than low-level optimizations for dataflow architectures. We show that FLOWER allows to synthesize efficient implementations for high-performance streaming applications targeting System-on-Chip and FPGA accelerator cards, in the context of image processing and computer vision.

BibTeX
@inproceedings{amiri2021flower,
  author          = {Amiri, Puya and Pérard-Gayot, Arsène and Membarth, Richard and Slusallek, Philipp and Leißa, Roland and Hack, Sebastian},
  address         = {Auckland, New Zealand},
  booktitle       = {Proceedings of the 2021 International Conference on Field-Programmable Technology (ICFPT)},
  title           = {{FLOWER}: A Comprehensive Dataflow Compiler for High-Level Synthesis},
  pages           = {1--9},
  %year            = 2021,
  %month           = dec,
  date            = {2021-12-06/2021-12-10},
  doi             = {10.1109/ICFPT52863.2021.9609930},
  organization    = {IEEE}
}