Generating FPGA-based Image Processing Accelerators with Hipacc

Invited Paper

Domain-Specific Languages (DSLs) provide a high-level and domain-specific abstraction to describe algorithms within a certain domain concisely. Since a DSL separates the algorithm description from the actual target implementation, it offers a high flexibility among heterogeneous hardware targets, such as CPUs and GPUs. With the recent uprise of promising High-Level Synthesis (HLS) tools, like Vivado HLS and Altera OpenCL, FPGAs are becoming another attractive target architecture. Particularly in the domain of image processing, applications often come with stringent requirements regarding performance, energy efficiency, and power, for which FPGA have been proven to be among the most suitable architectures.

In this work, we present the Hipacc framework, a DSL and source-to-source compiler for image processing. We show that domain knowledge can be captured to generate tailored implementations for C-based HLS from a common high-level DSL description targeting FPGAs. Our approach includes FPGA-specific memory architectures for handling point and local operators, as well as several high-level transformations. We evaluate our approach by comparing the resulting hardware accelerators to GPU implementations, generated from exactly the same DSL source code.

  author       = {Reiche, Oliver and Özkan, Mehmet Akif and Membarth, Richard and Teich, Jürgen and Hannig, Frank},
  address      = {Irvine, CA, USA},
  booktitle    = {Proceedings of the International Conference On Computer Aided Design (ICCAD)},
  title        = {{Generating FPGA-based Image Processing Accelerators with Hipacc}},
  pages        = {1026--1033},
  year         = 2017,
  month        = nov,
  date         = {2017-11-13/2017-11-16},
  note         = {{Invited Paper}},
  doi          = {10.1109/ICCAD.2017.8203894},
  organization = {IEEE}